The present invention relates to data processing systems and, more particularly, to a bus controller for a data processing system in which data is transferred between a bus master and a bus slave of a plurality of different data port widths via a bus.
Japanese Patent Application Kokai No. 61-502565 discloses a data processor having a dynamic bus sizing capability. A conventional bus controller having a bus sizing function such as shown in the above Japanese patent is shown in FIG. 10. A bus controller 20 is connected between a data processor 10 as a bus master and a memory unit 30 as a bus slave. The data processor 10 has a 32-bit data port.
The data processor 10 executes instructions specified by the user. Each instruction is read from the memory unit 30 in a predetermined order. In execution of each instruction, the data processor 10 can perform specified operations on data of an 8-bit (byte), 16-bit (half word), or 32-bit (word) size. Most of these data operands are read from or written into the memory unit 30 via a bus.
The memory unit or bus slave 30 can have a data port smaller than that of the data processor 10. For example, peripheral equipment of 8 or 16 bits can be connected to the bus, or part of the memory unit can be connected to a remote data processor 10 via a data bus of a smaller size. Even in the same port size, the operand requested by the data processor 10 can be at an address which is not aligned to the data port of a bus slave. Where operands are not aligned, or the port size is different between a data processor and a memory unit, the bus controller 20 must adjust the position of data on the bus for correctly transferring the requested data or instruction operand.
In operation, the data processor 10 requests operand transfer by asserting the bus cycle start signal of a bus timing signal for the bus controller 20, and indicates the direction of operand transfer with the read cycle/write cycle signal (R/W) of a bus cycle type signal and the size of a transfer operand with a data size signal. Also, it provides a 32-bit master address signal MA (0:31), into or from which the operand is transferred.
The data processor 10 requests an operand write operation as follows. Upon reception of a bus cycle start signal, the bus controller 20 outputs master address information at the address signal line of a slave for transfer to the memory unit 30. The same applies for bus cycle type and data size signals. After a predetermined period of time, the bus controller 20 asserts the address strobe signal (AS) of a slave bus timing signal to indicate that a valid operand address is on the slave address signal line.
The bus controller 20 also determines a connection condition between the master and slave data buses based on information about two insignificant bits of a master address signal and a data size signal and provides output data to an appropriate byte on the slave data bus. Furthermore, it asserts the data strobe signal (DS) of a bus timing signal, informing the memory unit 30 that the operand on the data bus is valid.
Upon reception of the AS, the memory unit 30 decodes the address signal. If it finds itself selected, it prepares to latch the operand. In order to make correct transfer, the memory unit 30 positions the significant byte of a data port on the significant byte of a data bus. Consequently, upon reception of the DS, it is able to latch at least the significant byte of an operand during the first bus cycle of an operand cycle.
Then, the memory unit 30 outputs a port size and transfer completion signal to inform the data processor 10 of the transfer completion. The port size and transfer completion signal also indicates the data port size of the memory unit 30 to which the transfer is made.
Based on the information about the data size signal, two insignificant bits of the address signal, and the port size from the memory unit 30, the bus controller 20 is able to recognize which part of the operand has been transferred and which part remains untransferred. If there is the remaining part of unreceived operand, the size is determined. If an additional bus cycle is necessary for completing the operand cycle, the bus controller 20 recalculates the address signal of two insignificant bits for the remaining part of the operand.
In this way, the bus controller 20 operates until all the requested operands are latched in the memory unit 30. When all the operands are transferred, the bus controller outputs a master transfer completion signal to the data processor 10.
The write operand cycle is summarized as follows.
Bus Master and Bus Controller
1) Set the read cycle/write cycle (R/W) write cycle.
2) Output an address signal.
3) Output a data size signal.
4) Assert an address strobe (AS).
5) Determine the position of a data output based on information about two insignificant bits of an address and a data size and output operand data.
6) Assert a data strobe (DS).
Bus Slave
1) Decode an address signal.
2) Latch an operand byte on the data bus.
3) Assert a port size and transfer a completion signal.
Bus Master and Bus Controller
7) Negate the DS.
8) Negate the AS.
9) Stop outputting an operand on the data bus.
Bus Slave
4) Negate the port size and transfer completion signal.
Bus Master and Bus Controller
10) If not all of the operands are transferred because of the port size, recalculate the address and size and return to the step 1)
11) Otherwise, complete the operand cycle.
The read cycle, on the other hand, is summarized as follows.
Bus Master and Bus Controller
1) Set the R/W signal to the read cycle.
2) Output an address signal.
3) Output a data size signal.
4) Assert an AS.
5) Assert a DS.
Bus Slave
1) Decode the address signal.
2) Output data at the data bus position corresponding to the address signal and data size signal.
3) Assert a port size and transfer complete signal.
Bus Master and Bus Controller
6) Latch the transferred data at the byte position determined by the address signal, port size, and data size.
7) Negate the DS.
8) Negate the AS.
Bus Slave
4) Stop outputting data to the data bus.
5) Negate the port size and transfer completion signal.
Bus Master and Bus Controller
9) If not all of the operands are transferred, recalculate the address and data size and return to the step 1).
10) Otherwise, complete the operand cycle.
In this way, the bus controller 20 performs dynamic sizing of a communications bus for each cycle based on the port size information from the bus slave.
However, it is necessary to output both the data transfer completion signal and the port size response on the same signal line depending on the bus slave, bringing about the following problems.
In order to increase the bus transfer speed, the data transfer completion signal should be sampled toward the end of a bus cycle, but it should be sampled earlier because it is necessary to determined the byte position at which data is written in the register based on the port size and then recalculate the address before start of the next bus cycle. Consequently, a high-speed circuit has been demanded to sample both the data transfer completion signal and the port size response signal with the same timing for bus cycling.
Also, it has been difficult to make a wait controller which operates independently of the bus slave and asserts the data transfer completion signal with predetermined timing corresponding to the address area.